NUC472_NUC442_BSP V3.03.005
The Board Support Package for NUC472/NUC442
Macros | Functions | Variables
clk.h File Reference

NUC472/NUC442 CLK Header File. More...

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Macros

#define FREQ_500MHZ   500000000
 
#define FREQ_250MHZ   250000000
 
#define FREQ_200MHZ   200000000
 
#define FREQ_125MHZ   125000000
 
#define FREQ_72MHZ   72000000
 
#define FREQ_50MHZ   50000000
 
#define FREQ_25MHZ   25000000
 
#define FREQ_24MHZ   24000000
 
#define FREQ_22MHZ   22000000
 
#define FREQ_32KHZ   32000
 
#define FREQ_10KHZ   10000
 
#define CLK_PLLCTL_PLLSRC_HIRC
 
#define CLK_PLLCTL_PLLSRC_HXT
 
#define CLK_PLLCTL_NR(x)
 
#define CLK_PLLCTL_NF(x)
 
#define CLK_PLLCTL_NO_1
 
#define CLK_PLLCTL_NO_2
 
#define CLK_PLLCTL_NO_4
 
#define CLK_PLLCTL_50MHz_HIRC
 
#define CLK_PLLCTL_48MHz_HIRC
 
#define CLK_PLLCTL_36MHz_HIRC
 
#define CLK_PLLCTL_32MHz_HIRC
 
#define CLK_PLLCTL_24MHz_HIRC
 
#define CLK_PLL2CTL_PLL2DIV(x)
 
#define CLK_CLKSEL0_HCLKSEL_HXT
 
#define CLK_CLKSEL0_HCLKSEL_LXT
 
#define CLK_CLKSEL0_HCLKSEL_PLL
 
#define CLK_CLKSEL0_HCLKSEL_LIRC
 
#define CLK_CLKSEL0_HCLKSEL_PLL2
 
#define CLK_CLKSEL0_HCLKSEL_HIRC
 
#define CLK_CLKSEL0_STCLKSEL_HXT
 
#define CLK_CLKSEL0_STCLKSEL_LXT
 
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
 
#define CLK_CLKSEL0_STCLKSEL_HCLK   (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)
 
#define CLK_CLKSEL0_PCLKSEL_HCLK
 
#define CLK_CLKSEL0_PCLKSEL_HCLK_DIV2
 
#define CLK_CLKSEL0_USBHSEL_PLL
 
#define CLK_CLKSEL0_USBHSEL_PLL2
 
#define CLK_CLKSEL0_CAPSEL_HXT
 
#define CLK_CLKSEL0_CAPSEL_PLL
 
#define CLK_CLKSEL0_CAPSEL_HCLK
 
#define CLK_CLKSEL0_CAPSEL_HIRC
 
#define CLK_CLKSEL0_ICAPSEL_HXT
 
#define CLK_CLKSEL0_ICAPSEL_PLL
 
#define CLK_CLKSEL0_ICAPSEL_HCLK
 
#define CLK_CLKSEL0_ICAPSEL_HIRC
 
#define CLK_CLKSEL0_SDHSEL_HXT
 
#define CLK_CLKSEL0_SDHSEL_PLL
 
#define CLK_CLKSEL0_SDHSEL_HCLK
 
#define CLK_CLKSEL0_SDHSEL_HIRC
 
#define CLK_CLKSEL1_WDTSEL_HXT
 
#define CLK_CLKSEL1_WDTSEL_LXT
 
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048
 
#define CLK_CLKSEL1_WDTSEL_LIRC
 
#define CLK_CLKSEL1_ADCSEL_HXT
 
#define CLK_CLKSEL1_ADCSEL_PLL
 
#define CLK_CLKSEL1_ADCSEL_PCLK
 
#define CLK_CLKSEL1_ADCSEL_HIRC
 
#define CLK_CLKSEL1_EADCSEL_HXT
 
#define CLK_CLKSEL1_EADCSEL_PLL
 
#define CLK_CLKSEL1_EADCSEL_PCLK
 
#define CLK_CLKSEL1_EADCSEL_HIRC
 
#define CLK_CLKSEL1_SPI0SEL_PLL
 
#define CLK_CLKSEL1_SPI0SEL_PCLK
 
#define CLK_CLKSEL1_SPI1SEL_PLL
 
#define CLK_CLKSEL1_SPI1SEL_PCLK
 
#define CLK_CLKSEL1_SPI2SEL_PLL
 
#define CLK_CLKSEL1_SPI2SEL_PCLK
 
#define CLK_CLKSEL1_SPI3SEL_PLL
 
#define CLK_CLKSEL1_SPI3SEL_PCLK
 
#define CLK_CLKSEL1_TMR0SEL_HXT
 
#define CLK_CLKSEL1_TMR0SEL_LXT
 
#define CLK_CLKSEL1_TMR0SEL_PCLK
 
#define CLK_CLKSEL1_TMR0SEL_EXT
 
#define CLK_CLKSEL1_TMR0SEL_LIRC
 
#define CLK_CLKSEL1_TMR0SEL_HIRC
 
#define CLK_CLKSEL1_TMR1SEL_HXT
 
#define CLK_CLKSEL1_TMR1SEL_LXT
 
#define CLK_CLKSEL1_TMR1SEL_PCLK
 
#define CLK_CLKSEL1_TMR1SEL_EXT
 
#define CLK_CLKSEL1_TMR1SEL_LIRC
 
#define CLK_CLKSEL1_TMR1SEL_HIRC
 
#define CLK_CLKSEL1_TMR2SEL_HXT
 
#define CLK_CLKSEL1_TMR2SEL_LXT
 
#define CLK_CLKSEL1_TMR2SEL_PCLK
 
#define CLK_CLKSEL1_TMR2SEL_EXT
 
#define CLK_CLKSEL1_TMR2SEL_LIRC
 
#define CLK_CLKSEL1_TMR2SEL_HIRC
 
#define CLK_CLKSEL1_TMR3SEL_HXT
 
#define CLK_CLKSEL1_TMR3SEL_LXT
 
#define CLK_CLKSEL1_TMR3SEL_PCLK
 
#define CLK_CLKSEL1_TMR3SEL_EXT
 
#define CLK_CLKSEL1_TMR3SEL_LIRC
 
#define CLK_CLKSEL1_TMR3SEL_HIRC
 
#define CLK_CLKSEL1_UARTSEL_HXT
 
#define CLK_CLKSEL1_UARTSEL_PLL
 
#define CLK_CLKSEL1_UARTSEL_HIRC
 
#define CLK_CLKSEL1_CLKOSEL_HXT
 
#define CLK_CLKSEL1_CLKOSEL_LXT
 
#define CLK_CLKSEL1_CLKOSEL_HCLK
 
#define CLK_CLKSEL1_CLKOSEL_HIRC
 
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048
 
#define CLK_CLKSEL1_WWDTSEL_LIRC
 
#define CLK_CLKSEL2_PWM0CH01SEL_HXT
 
#define CLK_CLKSEL2_PWM0CH01SEL_LXT
 
#define CLK_CLKSEL2_PWM0CH01SEL_PCLK
 
#define CLK_CLKSEL2_PWM0CH01SEL_HIRC
 
#define CLK_CLKSEL2_PWM0CH01SEL_LIRC
 
#define CLK_CLKSEL2_PWM0CH23SEL_HXT
 
#define CLK_CLKSEL2_PWM0CH23SEL_LXT
 
#define CLK_CLKSEL2_PWM0CH23SEL_PCLK
 
#define CLK_CLKSEL2_PWM0CH23SEL_HIRC
 
#define CLK_CLKSEL2_PWM0CH23SEL_LIRC
 
#define CLK_CLKSEL2_PWM0CH45SEL_HXT
 
#define CLK_CLKSEL2_PWM0CH45SEL_LXT
 
#define CLK_CLKSEL2_PWM0CH45SEL_PCLK
 
#define CLK_CLKSEL2_PWM0CH45SEL_HIRC
 
#define CLK_CLKSEL2_PWM0CH45SEL_LIRC
 
#define CLK_CLKSEL2_PWM1CH01SEL_HXT
 
#define CLK_CLKSEL2_PWM1CH01SEL_LXT
 
#define CLK_CLKSEL2_PWM1CH01SEL_PCLK
 
#define CLK_CLKSEL2_PWM1CH01SEL_HIRC
 
#define CLK_CLKSEL2_PWM1CH01SEL_LIRC
 
#define CLK_CLKSEL2_PWM1CH23SEL_HXT
 
#define CLK_CLKSEL2_PWM1CH23SEL_LXT
 
#define CLK_CLKSEL2_PWM1CH23SEL_PCLK
 
#define CLK_CLKSEL2_PWM1CH23SEL_HIRC
 
#define CLK_CLKSEL2_PWM1CH23SEL_LIRC
 
#define CLK_CLKSEL2_PWM1CH45SEL_HXT
 
#define CLK_CLKSEL2_PWM1CH45SEL_LXT
 
#define CLK_CLKSEL2_PWM1CH45SEL_PCLK
 
#define CLK_CLKSEL2_PWM1CH45SEL_HIRC
 
#define CLK_CLKSEL2_PWM1CH45SEL_LIRC
 
#define CLK_CLKSEL3_SC0SEL_HXT
 
#define CLK_CLKSEL3_SC0SEL_PLL
 
#define CLK_CLKSEL3_SC0SEL_PCLK
 
#define CLK_CLKSEL3_SC0SEL_HIRC
 
#define CLK_CLKSEL3_SC1SEL_HXT
 
#define CLK_CLKSEL3_SC1SEL_PLL
 
#define CLK_CLKSEL3_SC1SEL_PCLK
 
#define CLK_CLKSEL3_SC1SEL_HIRC
 
#define CLK_CLKSEL3_SC2SEL_HXT
 
#define CLK_CLKSEL3_SC2SEL_PLL
 
#define CLK_CLKSEL3_SC2SEL_PCLK
 
#define CLK_CLKSEL3_SC2SEL_HIRC
 
#define CLK_CLKSEL3_SC3SEL_HXT
 
#define CLK_CLKSEL3_SC3SEL_PLL
 
#define CLK_CLKSEL3_SC3SEL_PCLK
 
#define CLK_CLKSEL3_SC3SEL_HIRC
 
#define CLK_CLKSEL3_SC4SEL_HXT
 
#define CLK_CLKSEL3_SC4SEL_PLL
 
#define CLK_CLKSEL3_SC4SEL_PCLK
 
#define CLK_CLKSEL3_SC4SEL_HIRC
 
#define CLK_CLKSEL3_SC5SEL_HXT
 
#define CLK_CLKSEL3_SC5SEL_PLL
 
#define CLK_CLKSEL3_SC5SEL_PCLK
 
#define CLK_CLKSEL3_SC5SEL_HIRC
 
#define CLK_CLKSEL3_I2S0SEL_HXT
 
#define CLK_CLKSEL3_I2S0SEL_PLL
 
#define CLK_CLKSEL3_I2S0SEL_PCLK
 
#define CLK_CLKSEL3_I2S0SEL_HIRC
 
#define CLK_CLKSEL3_I2S1SEL_HXT
 
#define CLK_CLKSEL3_I2S1SEL_PLL
 
#define CLK_CLKSEL3_I2S1SEL_PCLK
 
#define CLK_CLKSEL3_I2S1SEL_HIRC
 
#define CLK_CLKDIV0_HCLK(x)
 
#define CLK_CLKDIV0_USB(x)
 
#define CLK_CLKDIV0_UART(x)
 
#define CLK_CLKDIV0_ADC(x)
 
#define CLK_CLKDIV0_SDH(x)
 
#define CLK_CLKDIV1_SC0(x)
 
#define CLK_CLKDIV1_SC1(x)
 
#define CLK_CLKDIV1_SC2(x)
 
#define CLK_CLKDIV1_SC3(x)
 
#define CLK_CLKDIV2_SC4(x)
 
#define CLK_CLKDIV2_SC5(x)
 
#define CLK_CLKDIV3_CAP(x)
 
#define CLK_CLKDIV3_VSENSE(x)
 
#define CLK_CLKDIV3_EMAC(x)
 
#define MODULE_APBCLK(x)
 
#define MODULE_CLKSEL(x)
 
#define MODULE_CLKSEL_Msk(x)
 
#define MODULE_CLKSEL_Pos(x)
 
#define MODULE_CLKDIV(x)
 
#define MODULE_CLKDIV_Msk(x)
 
#define MODULE_CLKDIV_Pos(x)
 
#define MODULE_IP_EN_Pos(x)
 
#define MODULE_NoMsk
 
#define NA
 
#define MODULE_APBCLK_ENC(x)   (((x) & 0x03) << 30)
 
#define MODULE_CLKSEL_ENC(x)   (((x) & 0x03) << 28)
 
#define MODULE_CLKSEL_Msk_ENC(x)   (((x) & 0x07) << 25)
 
#define MODULE_CLKSEL_Pos_ENC(x)   (((x) & 0x1f) << 20)
 
#define MODULE_CLKDIV_ENC(x)   (((x) & 0x03) << 18)
 
#define MODULE_CLKDIV_Msk_ENC(x)   (((x) & 0xff) << 10)
 
#define MODULE_CLKDIV_Pos_ENC(x)   (((x) & 0x1f) << 5)
 
#define MODULE_IP_EN_Pos_ENC(x)   (((x) & 0x1f) << 0)
 
#define PDMA_MODULE
 
#define ISP_MODULE
 
#define EBI_MODULE
 
#define USBH_MODULE
 
#define EMAC_MODULE
 
#define SDH_MODULE
 
#define CRC_MODULE
 
#define CAP_MODULE
 
#define SEN_MODULE
 
#define USBD_MODULE
 
#define CRPT_MODULE
 
#define WDT_MODULE
 
#define WWDT_MODULE
 
#define RTC_MODULE
 
#define TMR0_MODULE
 
#define TMR1_MODULE
 
#define TMR2_MODULE
 
#define TMR3_MODULE
 
#define CLKO_MODULE
 
#define ACMP_MODULE
 
#define I2C0_MODULE
 
#define I2C1_MODULE
 
#define I2C2_MODULE
 
#define I2C3_MODULE
 
#define SPI0_MODULE
 
#define SPI1_MODULE
 
#define SPI2_MODULE
 
#define SPI3_MODULE
 
#define UART0_MODULE
 
#define UART1_MODULE
 
#define UART2_MODULE
 
#define UART3_MODULE
 
#define UART4_MODULE
 
#define UART5_MODULE
 
#define CAN0_MODULE
 
#define CAN1_MODULE
 
#define OTG_MODULE
 
#define ADC_MODULE
 
#define I2S0_MODULE
 
#define I2S1_MODULE
 
#define PS2_MODULE
 
#define SC0_MODULE
 
#define SC1_MODULE
 
#define SC2_MODULE
 
#define SC3_MODULE
 
#define SC4_MODULE
 
#define SC5_MODULE
 
#define I2C4_MODULE   ((2UL<<30)|(0<<28)|(0<<25) |( 0<<20)|(0<<18)|(MODULE_NoMsk<<10)|( 0<<5)|CLK_APBCLK1_I2C4CKEN_Pos)
 
#define PWM0CH01_MODULE
 
#define PWM0CH23_MODULE
 
#define PWM0CH45_MODULE
 
#define PWM1CH01_MODULE
 
#define PWM1CH23_MODULE
 
#define PWM1CH45_MODULE
 
#define QEI0_MODULE
 
#define QEI1_MODULE
 
#define ECAP0_MODULE
 
#define ECAP1_MODULE
 
#define EPWM0_MODULE
 
#define EPWM1_MODULE
 
#define OPA_MODULE
 
#define EADC_MODULE
 
#define CLK_TIMEOUT_ERR
 

Functions

void CLK_DisableCKO (void)
 Disable frequency output function. More...
 
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
 
void CLK_PowerDown (void)
 Enter to Power-down mode. More...
 
void CLK_Idle (void)
 Enter to Idle mode. More...
 
uint32_t CLK_GetHXTFreq (void)
 Get external high speed crystal clock frequency. More...
 
uint32_t CLK_GetLXTFreq (void)
 Get external low speed crystal clock frequency. More...
 
uint32_t CLK_GetHCLKFreq (void)
 Get HCLK frequency. More...
 
uint32_t CLK_GetPCLKFreq (void)
 This function get PCLK frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetCPUFreq (void)
 Get CPU frequency. More...
 
uint32_t CLK_GetPLLClockFreq (void)
 This function get PLL frequency. The frequency unit is Hz. More...
 
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 Set HCLK frequency. More...
 
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider. More...
 
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider. More...
 
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 This function set SysTick clock source. More...
 
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 This function enable clock source. More...
 
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 This function disable clock source. More...
 
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 This function enable module clock. More...
 
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 This function disable module clock. More...
 
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 This function set PLL frequency. More...
 
void CLK_DisablePLL (void)
 This function disable PLL. More...
 
int32_t CLK_SysTickDelay (uint32_t us)
 This function execute delay function. More...
 
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status. More...
 
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter. More...
 
void CLK_DisableSysTick (void)
 Disable System Tick counter. More...
 

Variables

int32_t g_CLK_i32ErrCode
 

Detailed Description

NUC472/NUC442 CLK Header File.

Version
V1.0 $Revision 1 $
Date
15/11/19 10:06a
Note
SPDX-License-Identifier: Apache-2.0 Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.

Definition in file clk.h.